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video clock synthesizer mds 1527 g revision 110905 ics reserves the right to make cha nges in the preliminary device data identified in this publication withou t notice. ics advises its customers to obtain the latest version of all devi ce data to verify that information being relied upon is current and accurate. integrated circuit systems ics1527 video clock synthesizer features ? lead-free packaging (pb-free) ? low jitter (typical 27 ps short term jitter) ? lvcmos single-ended clock outputs ? 60/110 mhz speed grades available ? uses 3.3 v power supply ? 5 volt tolerant inputs (hsync, vsync) ? coast (ignore hsync) capability via vsync pin ? industry standard i 2 c-bus programming interface ? pll lock detection via i 2 c or lock output pin ? 16-pin tssop package applications ? frequency synthesis ? lcd monitors, video projectors and plasma displays ? genlocking multiple video subsystems pin configurati on (16-pin tssop) vddd 1 vssd sda scl vsync i2cadr vdda vssq vddq clk hsync_out lock vsync _out hsync vssa 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 extfb general description the ics1527 is a low-cost, high-performance frequency generator. it is suited to general purpose phase controlled clock synthesis as well as line-locked and genlocked high-resolution video applications. using ics? s advanced low-voltage cmos mixed-mode technolo gy, the ics1527 is an effective clock synthesizer that supports video projectors and displays at resolutions from vga to beyond xga. the ics1527 offers single-ended clock outputs to 60 or 110 mhz. the hsync_ out, and vsync_out pins provide the regenerated versions of the hsync and vsync inputs synchronous to the clk output. the advanced pll uses either its internal programmable feedback divider or an external divider. the device is programmed by a standard i 2 c-bus? serial interface and is available in a tssop16 package. ics1527 functional diagram hsync vsync i 2 c hsync_out vsync_out extfb external divider clk ics1527 idt? / ics? video clock synthesizer ics1527 1 data sheet ics1527
idt? / ics? video clock synthesizer ics1527 2 ics1527 video clock synthesizer tsd mds 1527 g 2 revision 110905 integrated circuit systems, 525 race stre et, san jose, ca 95126, tel (408) 297-1201 www.icst.com section 1 overview ics1527 data sheet section 1 overview the ics1527 is a user-programmable, high-performance general purpose clock generator. it is intended for graphics system line-locked and genlocked applications, and provides the clock signals required by high-performance analog-to-digital converters. the ics1527 has the ability to operate in line-locked mode with the hsync input. 1.1 phase-locked loop the phase-locked loop has a very wide input frequency range (8 khz to 100 mhz). not only is the ics1527 an excellent, general purpose clock synthesizer, but it is also capable of line-locked operation. refer to the block diagram below. the heart of the ics1527 is a voltage controlled oscillator (vco). the vco speed is controlled by the voltage on the loop filter. this voltage will be described later in this section. the vco?s clock output is first passed through the vco divider (vcod). the vcod allows the vco to operate at higher speeds than the required output clock. note : under normal, locked operation the vcod has no effect on the speed of the output clocks, just the vco frequency. the output of the vcod is the full speed output frequency seen on the clk. this clock is then sent through the 12-bit internal feedback divider (fd). the feedback divider controls how many clocks are seen during every cycle of the input reference. the phase frequency detector (pfd) then compares the feedback to the input and controls the filter voltage by enabling and disabling the charge pump. the charge pump has programmab le current drive and will source and sink current as appropriate to keep the input and the hsync_out output aligned. the input hsync and vsync can be conditioned by a high-performance schmitt-trigger by sharpening the rising/falling edge. the hsync_out and vsync_out signals are aligned with the output clock (clk) via a set of flip flops. 1.2 output driver s and logic inputs the ics1527 uses low-voltage ttl (lvttl) inputs and lvcmos outputs, operati ng at the 3.3 v supply voltage. the lvttl inputs are 5 v tolerant. the lvcmos drive resistive terminations or transmission lines. 1.3 automatic power-on reset detection the ics1527 has automatic power-on reset detection (por) circuitry and it resets itself if the supply voltage drops below threshold values. no external connection to a reset signal is required. figure 1-1 simplified block diagram note: polarity controls and other circuit elemen ts are not shown in above diagram for simplicity pfd cp vco vcod 2,4,8,16 hsync flip-flop vsync clk hsync_out vsync_out fd 12..4103 flip-flop extfb
idt? / ics? video clock synthesizer ics1527 3 ics1527 video clock synthesizer tsd mds1527 g 3 revision 110905 integrated circuit systems, 525 race stre et, san jose, ca 95126, tel (408) 297-1201 www.icst.com section 1 overview ics1527 data sheet 1.4 i 2 c bus serial interface the ics1527 uses a 5 volt tolerant, industry-standard i 2 c-bus serial interface that runs at either low-speed (100 khz) or high-speed (400 khz). the interface uses 12 word addresses for control and status: one write-only, eight read/write, and three read-only addresses. two ics1527 devices can sit on the same i 2 c bus, each selected by the master according to the state of the i2cadr pin. the 7 bit device address is 0100110 (binary) when i2cadr is low. the device address is 0100111 (binary) when i2cadr is high. see section 4, ?programming?
idt? / ics? video clock synthesizer ics1527 4 ics1527 video clock synthesizer tsd mds 1527 g 4 revision 110905 integrated circuit systems, 525 race stre et, san jose, ca 95126, tel (408) 297-1201 www.icst.com section 2 pin descriptions ics1527 data sheet section 2 pin descriptions notes: 1. these lvttl inputs are 5 v tolerant. 2. connect to ground if unused. table 2-1 ics1527 pin descriptions pin no. pin name type description comments notes 1 vssd power digital ground 2sda in/out serial data i 2 c-bus 1 3scl in serial clock i 2 c-bus 1 4 vsync in vertical sync 1 & 2 5 extfb in external feedback from external divider 1 & 2 6hsync in horizontal sync clock input to pll 1 & 2 7vdda power analog supply power for analog circuitry 8 vssa power analog ground ground for analog circuitry 9i2cadr in i 2 c device address chip i 2 c address select 10 lock lvcmos out lock pll lock 11 hsync_out lvcmos out hsync output schmitt-trigger filtered hsync realigned with the output pixel clock 12 clk lvcmos out pixel clock output lvcmos dr iver for full-speed clock 13 vddq power output driver supply power for output drivers 14 vsync_out lvcmos out vsync output schmitt- trigger filtered vsync realigned with the output pixel clock 15 vssq power output driver ground ground for output drivers 16 vddd power digital supply power for digital sections
mds1527 g 5 revision 110905 integrated circuit systems, 525 race stre et, san jose, ca 95126, tel (408) 297-1201 www.icst.com section 3 register map summary ics1527 data sheet section 3 register map summary word address name access bit name bit # reset value description 00h input control r / w cpen 0 1 charge pump enable 0=external enable via vsync, 1=always enabled vsync_pol 1 0 vsync polarity (charge pump enable) requires 00h:0=0 0=coast (charge pump disabled) while vsync low, 1=coast (charge pump disabled) while vsync high hsync_pol 2 0 hsync polarity 0=rising edge, 1=falling edge fbk_pol 3 0 external feedback polarity 0=positive edge, 1=negative edge fbk_sel 4 0 external feedback select 0=internal feedback, 1=external reserved 5 0 reserved enpls 6 1 enable pll lock status output 0=disable, 1=enable reserved 7 0 reserved 01h loop control * r / w icp0-2 0-2 icp (charge pump current) bit 2,1,0 = {000 =1 a, 001 = 2 a, 010 = 4 a... 110 = 64 a, 111 = 128 a}. increasing the pf detector gain makes the loop respond faster, raising the loop bandwidth. the typical value when using the internal loop filter is 011. reserved 3 reserved vcod0-1 4-5 vco divider bit 5,4= {00 = 2, 01=4, 10=8, 11=16} reserved 6-7 reserved 02h fdbk div 0 * r / w fbd0-7 0-7 feedback divider lsbs (bits 0-7) 03h fdbk div 1 * r / w fbd8-11 0-3 feedback divider msbs (bits 8-11) divider setting = 12 bit word + 8 minimum 12 = 000000000100 maximum 4103 =111111111111 reserved 4-7 reserved 04h reserved reserved 0-7 0 reserved 05h schmitt- trigger * r / w schmitt control 0 1 schmitt-trigger control 0=schmitt-trigger, 1= no schmitt-trigger metal_rev 1-7 0 metal mask revision number 06h output enables r / w reserved 0 0 reserved oe 1 0 output enable for clk, hsync_out, vsync_out 0=high impedance (disabled), 1=enabled reserved 2-7 0 reserved idt? / ics? video clock synthesizer ics1527 5 ics1527 video clock synthesizer tsd
idt? / ics? video clock synthesizer ics1527 6 ics1527 video clock synthesizer tsd mds 1527 g 6 revision 110905 integrated circuit systems, 525 race stre et, san jose, ca 95126, tel (408) 297-1201 www.icst.com section 3 register map summary ics1527 data sheet 07h reserved reserved 0-6 reserved reserved 7 0 part requires a 0 for correct operation 08h reset write reserved 0-7 0 writing 5ah resets part and commits values written to word addresses 01h-03h and 05h 09-0fh reserved read reserved 0-7 reserved 10h chip ver read reserved 0-7 reserved 11h chip rev read chip rev 0-7 01 reserved 12h rd_reg read reserved 0 n/a reserved pll_lock 1 n/a pll lock status 0=unlocked, 1=locked reserved 2-7 0 reserved *. written values to these registers do not take effe ct immediately, but require a commit via register 08h word address name access bit name bit # reset value description
ics1527 video clock synthesizer tsd mds1527 g 7 revision 110905 integrated circuit systems, 525 race stre et, san jose, ca 95126, tel (408) 297-1201 www.icst.com section 4 programming ics1527 data sheet section 4 programming 4.1 industry-standard i 2 c serial bus: data format figure 4-1 ics1527 data format for i 2 c 2-wire serial bus notes: the ics1527 uses 16 byte pages (00h-0fh is the first pa ge, 10h-1fh is the second page). writing or reading beyond the end of page yields undefined results. the ics1527 has a device address of 010011b , where b is the state of the i2cadr pin. s t a r t 0 a c k a c k a c k single/multiple register write (page write) word address data (0) a c k data (n) s t o p ... s t a r t 0 a c k a c k a c k single/multiple register read word address data (0) data (n) s t o p ... 1 a c k n o a c k s t a r t a c k sequential single/multiple register read data (0) data (n) s t o p ... 1 a c k n o a c k s t a r t 0 1 0 0 1 1 b device address device address device address device address 0 1 0 0 1 1 b 0 1 0 0 1 1 b 0 1 0 0 1 1 b m aster drives line slave drives line idt? / ics? video clock synthesizer ics1527 7
idt? / ics? video clock synthesizer ics1527 8 ics1527 video clock synthesizer tsd mds 1527 g 8 revision 110905 integrated circuit systems, 525 race stre et, san jose, ca 95126, tel (408) 297-1201 www.icst.com section 5 ac/dc operating conditions ics1527 data sheet section 5 ac/dc op erating conditions 5.1 absolute maximum ratings table 5-1 lists absolute maximum ratings for the ics1527. stresses above these rati ngs can cause permanent damage to the device. these ratings, which are standard va lues for ics commercially rated parts, are stress ratings only. functional operation of the ics1527 at these or any other conditions above those indicated in the operational sections of the specifications is no t implied. exposure to absolute maximu m rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. table 5-2 environmental conditions table 5-3 dc characteristics table 5-1 ics1527 absolute maximum ratings item rating vdd, vdda, vddq (measured to vss) * *. measured with respect to vss. during normal operations, the vdd supply voltage for the ics1527 must remain within the recommended operating conditions. 4.3 v digital inputs vss ?0.3 v to 5.5 v analog inputs vss -0.3 v to 6.0 v analog outputs vssa ?0.3 v to vdda +0.3 v digital outputs vssq ?0.3 v to vddq +0.3 v storage temperature ?65c to +150c junction temperature 125c soldering temperature 260c esd susceptibility* > 2 kv ** **. electrostatic-sensitive devices. do not open or handle except in a static-free workstation. parameter min. typ. max. units ambient operating temperature 0 ? +70 c power supply voltage +3.0 +3.3 +3.6 v parameter symbol conditions min. max. units digital supply current iddd vddd = 3.6 v - 25 ma output driver supply current iddq vddd = 3.6 v no drivers enabled -6ma analog supply current idda vdda = 3.6 v - 5 ma power consumption 300 mw power-on-reset (por) threshold vss 1.8 v
idt? / ics? video clock synthesizer ics1527 9 ics1527 video clock synthesizer tsd mds1527 g 9 revision 110905 integrated circuit systems, 525 race stre et, san jose, ca 95126, tel (408) 297-1201 www.icst.com section 5 ac/dc operating conditions ics1527 data sheet table 5-4 ac characteristics parameter symbol min. typical max. units notes general vco frequency f vco 50 400 mhz vco gain k 165 mhz/v ac inputs extfb input frequency f extfb 8 10,000 khz extfb input high voltage v ih 2.0 v extfb input low voltage v il 1.0 v analog input (hsync/vsync) hsync input frequency f hsync 8 10,000 khz vsync input frequency f vsync 30 120 hz input high voltage v ih 1.7 5.5 v input low voltage v il vss - 0.3 1.1 v input hysteresis 0.2 0.8 v schmitt trigger active sda, scl digital inputs input high voltage v ih 25.5v input low voltage v il vss - 0.3 0.8 v i 2 caddr digital input input high voltage v ih 2 vdd+0.3 v input low voltage v il vss - 0.3 0.8 v sda digital output sda output low voltage v ol 0.4 v iout = 3 ma sda output high voltage v oh 6.0 v determined by external rset resistor lvcmos outputs (clk, hs ync_out, vsync_out, lock) output frequency, ics1527 -110glf f s 2.5 110 mhz vddd = 3.3 v output frequency, ics1527 -60glf f s 2.5 60 mhz vddd = 3.3 v duty cycle s dc 45 50 55 % 2 jitter, stj, rms stj 0.027 ns 30 khz input to 50 mhz output jitter, stj, pk-pk stj 0.200 ns jitter, input-output ioj 2.500 ns hsync in to clk out output low voltage v ol 0.4 v iout = 4 ma output high voltage v oh 2.4 v iout = -4 ma hsync to hsync_out propagation delay (without schmitt-trigger) 29ns 1
mds 1527 g 10 revision 110905 integrated circuit systems, 525 race stre et, san jose, ca 95126, tel (408) 297-1201 www.icst.com section 5 ac/dc operating conditions ics1527 data sheet note 1?measured between chosen edge of hsync (00h:2) and rising edge of output note 2?measured at 110 mhz, 3.3 vdc, 25 o c, 15 pf, unterminated hsync to hsync_out propagation delay (with schmitt-trigger) 610ns 1 clk to hsync_out/ vsync_out skew 1.0 ns clock and hsync_out/vsync_out transition time - rise t cr 1.0 1.5 ns 2 clock and hsync_out/vsync_out transition time - fall t cf 1.0 1.5 ns 2 lock transition time - rise t lr 3.0 ns 2 lock transition time - fall t lf 2.0 ns 2 parameter symbol min. typical max. units notes idt? / ics? video clock synthesizer ics1527 10 ics1527 video clock synthesizer tsd
idt? / ics? video clock synthesizer ics1527 11 ics1527 video clock synthesizer tsd mds1527 g 11 revision 110905 integrated circuit systems, 525 race stre et, san jose, ca 95126, tel (408) 297-1201 www.icst.com section 6 package outline and package dimensions ics1527 data sheet section 6 package outline and package dimensions 16-pin tssop 4.40 mm body, 0.65 mm pitch package dimensions are kept current with jedec publication no. 95 section 7 ordering information while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems (ics) assumes no responsibility for either its use or for the infringemen t of any patents or other righ ts of third parties, which wou ld result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliability, or other extraordina ry environmental requirements are not recomm ended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices o r critical medical instruments. part / order number marking shipping packaging package temperature ics1527g -60lf 1527g 2lf tubes 16-pin tssop 0 to +70 c ics1527g -60lft 1527g 2lf tape & reel 16-pin tssop 0 to +70 c ics1527g -110lf 1527g 1lf tubes 16-pin tssop 0 to +70 c ics1527g -110lft 1527g 1lf tape & reel 16-pin tssop 0 to +70 c index area 1 2 16 d e1 e seating plane a1 a a2 e - c - b aaa c c l millimeters inches symbol min max min max a--1.20--0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 4.90 5.1 0.193 0.201 e 6.40 basic 0.252 basic e1 4.30 4.50 0.169 0.177 e 0.65 basic 0.0256 basic l 0.45 0.75 0.018 0.030 0 8 0 8 aaa -- 0.10 -- 0.004
ics1527 video clock synthesizer tsd ics1890 auto-negotiation advertisement register (register 4 [0x04]) tsd mk1491-14 opti acpi firestar clock source tsd ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa xx-xxxx-xxxxx corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support clockhelp@idt.com 408-284-8200 innovate with idt and accelerate your future networks. contact: www.idt.com ics280 triple pll field prog. spread spectrum clock synthesizer tsd

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